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HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
Integrated Device Technology, Inc.
IDT71321SA/LA IDT71421SA/LA
FEATURES:
* High-speed access --Commercial: 20/25/35/45/55ns (max.) * Low-power operation --IDT71321/IDT71421SA --Active: 550mW (typ.) --Standby: 5mW (typ.) --IDT71321/421LA --Active: 550mW (typ.) --Standby: 1mW (typ.) * Two INT flags for port-to-port communications * MASTER IDT71321 easily expands data bus width to 16or-more-bits using SLAVE IDT71421 * On-chip port arbitration logic (IDT71321 only) * BUSY output flag on IDT71321; BUSY input on IDT71421 * Fully asynchronous operation from either port * Battery backup operation --2V data retention (LA Only) * TTL-compatible, single 5V 10% power supply * Available in popular hermetic and plastic packages * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT71321/IDT71421 are high-speed 2K x 8 DualPort Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT71421 "SLAVE" DualPort in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-morebit memory system applications results in full speed, errorfree operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200W from a 2V battery. The IDT71321/IDT71421 devices are packaged in a 52pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
FUNCTIONAL BLOCK DIAGRAM
OEL
R/WL
OER
R/WR
CEL
CER
I/O0L- I/O7L I/O Control I/O Control
I/O0R-I/O7R
BUSYL
(1,2)
BUSYR
Address Decoder
11
(1,2)
A10L A0L
MEMORY ARRAY
Address Decoder
A10R A0R
11
NOTES: 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT71421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270.
INTL
OEL
R/WL
CEL
ARBITRATION and INTERRUPT LOGIC
OER
R/WR
CER
(2)
INTR
(2)
2691 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2691/6
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (1,2)
BUSYL
R/WR R/WL
BUSYR
INT R
N/C N/C A10L
V CC CER R/W R BUSYR
A 10L INTL BUSYL R/WL CEL
INTR
NDEX A1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
A10R
A 0L OEL
INDEX
OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7R
2691 drw 02
NC GND I/O0R I/O1R
I/O4L I/O5L
I/O6L I/O7L
I/O2R I/O3R I/O4R I/O5R
I/O6R
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
87 6 5 4 3 2 1 52 51 50 49 48 47 46 45 9 44 10 43 11 42 12 IDT71321/421 41 13 J52-1 40 14 PLCC TOP VIEW (3) 39 15 38 16 37 17 36 18 35 19 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33
A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O 0L I/O 1L I/O 2L
OEL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V CC VCC
CER
A10R N/C N/C
INTL
CEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT71321/421 PN64-1 / PP64-1 64-PIN TQFP 64-PIN STQFP TOP VIEW (3)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OE R
A 0R A 1R A 2R A 3R A 4R A 5R A 6R N/C A 7R A 8R A 9R N/C N/C I/O7R I/O 6R
2691 drw 03
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Unit V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Ambient Temperature 0C to +70C GND 0V VCC 5.0V 10%
2691 tbl 02
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 -- -- Max. 5.5 0 6.0(2) 0.8 Unit V V V V
2691 tbl 03
2691 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1,3)
(TA = +25C, f = 1.0MHz) TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VIN = 3dV Max. Unit 9 pF 10 pF
2691 tbl 04 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 3. 11pF max. for other packages.
6.03
I/O 3L N/C I/O 4L I/O 5L I/O 6L I/O 7L N/C GND GND I/O 0R I/O1R I/O 2R I/O3R N/C I/O 4R I/O 5R
2
IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (VCC = 5.0V 10%)
71321X25 71321X35 71321X55 71321X100 71421X25 71421X35 71421X55 71421X100 Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit -- -- 110 280 -- -- 110 220 110 250 110 220 110 200 110 170 -- -- 30 30 -- -- 65 65 -- -- 1.0 0.2 -- -- 60 60 -- -- 65 45 -- -- 165 125 -- -- 15 5 -- -- 155 115 30 30 30 30 65 65 65 65 1.0 0.2 1.0 0.2 60 60 60 60 80 60 65 45 160 125 150 115 30 10 15 5 155 115 145 105 80 80 80 80 25 25 25 25 50 50 50 50 1.0 0.2 1.0 0.2 45 45 45 45 230 170 165 120 80 60 65 45 150 115 125 90 30 10 15 4 145 105 110 85 65 65 65 65 20 20 20 20 190 140 155 110 65 45 65 35 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 190 140 155 110 65 45 55 35 125 90 110 75 30 10 15 4 110 80 95 70 mA 71321X20
Symbol ICC
Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs)
Test Conditions
CEL
Version MIL. SA LA COM'L. SA LA
and CER = VIL, Outputs open, f = fMAX(2)
ISB1
CEL and CER = VIH, MIL. SA f = fMAX(2) LA COM'L. SA LA
mA
ISB2
VIL and VIH (5) Active Port Outputs Open, f = fMAX(2)
CE"A" = CE"B" =
MIL.
SA LA COM'L. SA LA
40 125 40 90 40 110 40 75 1.0 0.2 1.0 0.2 30 10 15 4
mA
ISB3
Full Standby Current CEL and (Both Ports - All CER > VCC -0.2V, CMOS Level Inputs VIN > VCC -0.2V or VIN < 0.2V,f = 0(3)
SA LA COM'L. SA LA
MIL.
mA
ISB4
Full Standby Current CE"A" < 0.2V and MIL. SA (5) (One Port - All CE"B" > VCC -0.2V LA CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA VIN < 0.2V, LA Active Port Outputs Open, f = fMAX(2)
40 110 40 85 40 100 40 70
mA
NOTES: 2689 tbl 05 1. 'X' in part numbers indicates power rating (SA or LA). 2. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc = 5V, TA=+25C for Typ. and is not production tested. Vcc DC = 100mA (Typ) 5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V 10%)
Symbol |lLl| |lLO| VOL VOL VOH Parameter Input Leakage Current(1) Output Leakage Current(1) Output Low Voltage (l/O0-l/O7) Open Drain Output Low Voltage (BUSY,INT) Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCCVIN = GND to VCC
CE
IDT71321SA IDT71421SA Min. Max. -- 10 10 0.4 0.5 --
lDT71321LA lDT71421LA Min. Max. -- -- -- -- 2.4 5 5 0.4 0.5 --
Unit A A V V V
2691 tbl 06
= VIH, VOUT = 0V to VCC -- VCC = 5.5VC-=S = VIH, VOUT = GND to VCC -- -- 2.4
lOL = 4mA lOL= 16mA lOL = 16mA lOH = -4mA
NOTE: 1. At Vcc < 2.0V leakages are undefined.
Supply CurrentVIN > VCC -0.2V or < 0.
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol VDR ICCDR tCDR
(3)
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Conditions VCC = 2.0V, CE > VCC - 0.2V VIN > VCC - 0.2V or VIN 0.2V COM'L.
Min. 2.0 -- 0 tRC(2)
71321LA/71421LA Max. Typ.(1) -- 100 -- -- 0 1500 -- --
Unit V A ns ns
2691 tbl 07
tR(3)
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization but not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1, 2, and 3
2691 tbl 08
VCC
4.5V tCDR
VDR 2.0V
4.5V tR
CE
VDR VIH VIH
2691 drw 04
5V 1250 DATA OUT 775 30pF
100pF for 55 and 100ns versions
5V 1250 DATA OUT 775 5pF
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * Including scope and jig.
5V 270
2691 drw 05
BUSY
or
INT
30pF
100pF for 55 and 100ns versions
Figure 3. BUSY and INT NT AC Output Test Load
6.03
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
Symbol Read Cycle tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold From Address Change Output Low-Z Time(1,3) Output High-Z Time(1,3) Chip Enable to Power Up Time(3) Chip Disable to Power Down Time(3) 20 -- -- 3 0 -- 0 -- -- 20 20 11 -- -- 10 -- 20 25 -- -- -- 3 0 -- 0 -- -- 25 25 12 -- -- 10 -- 25 35 -- -- -- 3 0 -- 0 -- -- 35 35 20 -- -- 15 -- 35 55 -- -- -- 3 5 -- 0 -- -- 55 55 25 -- -- 25 -- 50 100 -- -- -- 10 5 -- 0 -- -- 100 100 40 -- -- 40 -- 50 ns ns ns ns ns ns ns ns ns
2689 tbl 09
Parameter
71321X25 71321X35 71321X55 71321X100 71421X25 71421X35 71421X55 71421X100 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
71321X20
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. "X" in part numbers indicates power rating (SA or LA). 3. This parameter is guaranteed by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID tOH
BUSYOUT
tBDDH (2,3)
2691 drw 06
NOTES: 1. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincidental with CE transition Low. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (3)
tACE
CE
tAOE
(4)
tHZ (2)
OE
tLZ DATAOUT tLZ ICC CURRENT ISS
tPU
(1) (1)
tHZ VALID DATA tPD
(4)
(2)
50%
50%
2691 drw 07
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/W = VIH and the address is valid prior to or coincidental with CE transition Low. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
71321X20 Symbol Parameter Write Cycle tWC Write Cycle Time(2) tEW Chip Enable to End of Write tAW Address Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width(3) tWR Write Recovery Time tDW Data Valid to End of Write tHZ Output High-Z Time(1) tDH Data Hold Time tWZ Write Enabled to Output in High-Z(1) tOW Output Active From End of Write(1) Min. 20 15 15 0 15 0 10 -- 0 -- 0 Max. -- -- -- -- -- -- -- 10 -- 10 -- 71321X25 71421X25 Min. Max. 25 20 20 0 15 0 12 -- 0 -- 0 -- -- -- -- -- -- -- 10 -- 10 -- 71321X35 71321X55 71321X100 71421X35 71421X55 71421X100 Min. Max. Min. Max. Min. Max. 35 30 30 0 25 0 15 -- 0 -- 0 -- -- -- -- -- -- -- 15 -- 15 -- 55 40 40 0 30 0 20 -- 0 -- 0 -- -- -- -- -- -- -- 25 -- 30 -- 100 90 90 0 55 0 40 -- 0 -- 0 -- -- -- -- -- -- -- 40 -- 40 -- Unit ns ns ns ns ns ns ns ns ns ns ns
NOTES: 2692 tbl 10 1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA . 3. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 4. "X" in part numbers indicates power rating (SA or LA).
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8) W
tWC ADDRESS tHZ (7)
OE
tAW
CE
tAS R/W tWZ (7) DATA OUT
(4) (6)
tWP (2)
tWR
(3)
tHZ
(7)
tOW
(4)
tDW DATA IN
tDH
2691 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5) CE
tWC ADDRESS tAW
CE
tAS R/W tDW DATA IN
NOTES: 2691 drw 09 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
(6)
tEW
(2)
tWR
(3)
tDH
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)8M824S258M824S30
71321X20 Symbol Parameter Busy Timing (For Master lDT71321 Only) BUSY Access Time from Address tBAA BUSY Disable Time from Address tBDA BUSY Access Time from Chip Enable tBAC Min. Max. -- -- -- -- 12 -- -- 5 -- 5 0 12 -- -- 20 20 20 20 -- 50 35 -- 25 -- -- -- 40 30
7132158M824S4 71321X25 71321X35 71321X55 71321X100 71421X25 71421X35 71421X55 71421X100 Min. Max. Min. Max. Min. Max. Min. Max. Unit -- -- -- -- 15 -- -- 5 -- 5 0 15 -- -- 20 20 20 20 -- 50 35 -- 35 -- -- -- 50 35 -- -- -- -- 20 -- -- 5 -- 5 0 20 -- -- 20 20 20 20 -- 60 35 -- 35 -- -- -- 60 35 -- -- -- -- 20 -- -- 5 -- 5 0 20 -- -- 30 30 30 30 -- 80 55 -- 50 -- -- -- 80 55 -- -- -- -- 20 -- -- 5 -- 5 0 20 -- -- 50 50 50 50 -- 120 100 -- 65 -- -- 120 100 ns ns ns ns ns ns ns ns ns ns ns ns ns
BUSY Disable Time from Chip Enable tBDC Write Hold After BUSY(5) tWH Write Pulse to Data Delay(1) tWDD Write Data Valid to Read Data Delay(1) tDDD Arbitration Priority Set-up Time(2) tAPS BUSY Disable to Valid Data(3) tBDD Busy Timing (For Slave IDT71421 Only)e Write to BUSY Input(4) tWB
tWH tWDD tDDD Write Hold After BUSY(5) Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay(1)
NOTES: 2689 tbl 11 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'. 5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 6. "X" in part numbers indicates power rating (S or L).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY(2,3,4)
tWC ADDR'A' MATCH tWP R/W'A' tDW DATAIN'A' tAPS ADDR'B'
(1)
tDH
VALID
MATCH t BDA tBDD
BUSY'B'
tWDD DATAOUT'B' tDDD
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
2691 drw 10
VALID
6.03
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH BUSY(3)
tWP R/WL tWB
BUSYR
(1)
tWH R/WR
(2)
2691 drw 11
NOTES: 1. tWH must be met for both BUSY Input (IDT71421, slave) or Output (IDT71321, master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (1)
ADDR 'A' and 'B' ADDRESSES MATCH
CE'B'
tAPS
(2)
CE'A'
tBAC tBDC
BUSY'A'
2691 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
tRC ADDR'A' tAPS ADDR'B' tBAA tBDA
(2)
OR
tWC ADDRESSES DO NOT MATCH
ADDRESSES MATCH
BUSY'B'
2691 drw 13
NOTES: 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71321 only).
6.03
9
IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol Parameter Interrupt Timing tAS Address Set-up Time tWR Write Recovery Time tINS Interrupt Set Time tINR Interrupt Reset Time
NOTE: 1. "X" in part numbers indicates power rating (S or L).
71321X25 71421X25 Min. Max. 0 0 -- -- -- -- 25 25
71321X35 71421X35 Min. Max. 0 0 -- -- -- -- 25 25
8M824S25 71321X45 71421X45 Min. Max. 0 0 -- -- -- -- 35 35
8M824S308M824S35 71321X55 71421X55 Min. Max. Unit 0 0 -- -- -- -- 45 45 ns ns ns ns
2689 tbl 12
TIMING WAVEFORM OF INTERRUPT MODE SET INT
ADDR'A'
tWC INTERRUPT ADDRESS tAS (3)
(2) (4)
tWR
R/W'A' tINS
INT'B'
(3)
2691 drw 14
CLEAR INT
tRC ADDR'B' INTERRUPT CLEAR ADDRESS tAS (3)
OE'B'
tINR (3)
INT'B'
2691 drw 15
NOTES: 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.03
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES TABLE I -- NON-CONTENTION READ/WRITE CONTROL(4)
Left or Right Port(1) R/W CE D0-7 W OE X H X Z X L H H H L L L X X L H Function Port Disabled and in PowerDown Mode, ISB2 or ISB4 Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 DATAIN Data on Port Written Into Memory(2) DATAOUT Data in Memory Output on Port(3) Z High-impedance Outputs
2654 tbl 13
NOTES: 1. A0L - A10L A0R - A10R. 2. If BUSY = VIL, data is not written. 3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = High-impedance.
TABLE II -- INTERRUPT FLAG(1,4)
R/WL W L X X X
CEL CE
L X X L
Left Port
OEL OE
X X X L
A10L - A0L 7FF X X 7FE
INTL INT
X X L(3) H(2)
R/WR W X X L X
CER CE
X L L X
Right Port
OER OE
X L X X
A10L - A0R X 7FF 7FE X
INTR INT
L(2) H(3) X X
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
2654 tbl 14
NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE.
TABLE III -- ADDRESS BUSY ARBITRATION
Inputs Outputs
CEL CE
X H X L
CER CE
X X H L
A0L-A10L A0R-A10R
NO MATCH MATCH MATCH MATCH
BUSYL BUSYR BUSY (1) BUSY (1)
H H H (2) H H H (2)
Function Normal Normal Normal Write Inhibit(3)
2689 tbl 15 NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT71321 (master). Both are inputs for IDT71421 (slave). BUSYX outputs on the IDT71321 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving Low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin.
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT71321/IDT71421 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71321/ IDT71421 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted.
The Busy outputs on the IDT71321 RAM (Master) are open drain type outputs and require open drain resistors to operate. If these RAMs are being expanded in depth, then the Busy indication for the resulting array does not require the use of an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT71321/IDT71421 RAMs the Busy pin is an output if the part is Master (IDT71321), and the Busy pin is an input if the part is a Slave (IDT71421) as shown in Figure 4.
5V
INTERRUPTS
If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table. The left port clears the interrupt by access address location 7FE access when CER = OER = VIL, R/W is a "Don't Care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Table I for the interrupt operation.
270
MASTER Dual Port RAM
CE
BUSYR
BUSYL
SLAVE Dual Port RAM
CE
BUSYR
DECODER
5V
BUSYL
270
MASTER Dual Port RAM
CE
BUSYR
BUSYL BUSYL
SLAVE Dual Port RAM
CE
BUSYR BUSYR
2691 drw 16
BUSYL
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The Busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins High. If desired, unintended write operations can be prevented to a port by tying the Busy pin for that port Low.
Figure 4. Busy and chip enable routing for both width and depth expansion with IDT71321 (Master) and (Slave) IDT71421 RAMs.
If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The Busy arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
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IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0C to +70C)
J PF TF 20 25 35 45 55
52-pin PLCC (J52-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1)
Speed in nanoseconds
LA SA 71321 71421
Low Power Standard Power 16K (2K x 8-Bit) MASTER Dual-Port RAM w/ Interrupt 16K (2K x 8-Bit) SLAVE Dual-Port RAM w/ Interrupt
2691 drw 17
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